Fredrik Edman
Patent advisor
Implementation of a Highly Scalable Architecture for Fast Inversion of Triangular Matrices
Author
Summary, in English
highly scalable hardware architecture for fast inversion of
triangular matrices is presented. An integral part of
modem signal processing and communications
applications involves manipulation of large matrices.
Therefore, scalable and flexible hardware architectures
are increasingly sought for. In this paper, the traditional
triangular shaped array architecture with n(n+1)/2
communicating processors, with n being the number of
inputs, is mapped to a linear structure with only n
processors, The linear and the triangular shaped
architectures are compared in aspect of area consumption,
latencies, and maximum clocking speed. This paper also
show that the linear array structure avoids drawhacks such
as non-scalability, large area, and large power
consumption. The implementation is based on a
numerically stahle recurrence algorithm, which has
excellent properties for hardware implementation.
Department/s
- Department of Electrical and Information Technology
Publishing year
2003
Language
English
Pages
1137-1140
Links
Document type
Conference paper
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Conference name
IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2003
Conference date
2003-12-14 - 2003-12-17
Conference place
Sharjah, United Arab Emirates
Status
Published