Fredrik Edman
Patent advisor
Digital Hardware Aspects of Multiantenna Algorithms
Author
Summary, in English
The field of wireless communication is growing rapidly, with new requirements for the next generation of mobile and wireless communications technology. In order to achieve the capacities needed for future wireless systems, the design and implementation of advanced communications techniques such as multiantenna systems is required. These systems are realized by computationally complex algorithms, requiring new digital hardware architectures to be developed. The development of efficient and scalable hardware building blocks for realization of multiantenna algorithms is the focus of this thesis.
The first part of the thesis deals with the implementation of complex valued division. Two architectures implementing a numerically robust algorithm for computing complex valued division with standard arithmetic units are presented. The first architecture is based on a parallel computation scheme offering high throughput rate and low latency, while the second architecture is based on a resource conservative time-multiplexed computation scheme offering good throughput rate. The two implementations are compared to an implementation of a CORDIC based complex valued division.
The second part of the thesis discusses implementation aspects of fundamental matrix operations found in many multiantenna algorithms. Four matrix operations were implemented; triangular matrix inversion, QR-decomposition, matrix inversion, and singular value decomposition. Matrix operations are usually implemented using large arrays of processors, which are difficult to scale and consume a lot of resources. In this thesis a method based on the data flow was applied to map the algorithms to scalable linear arrays. An even more resource conservative design based on a single processing element was also derived. All the architectures are capable of handling complex valued data necessary for the implementation of communication algorithms.
In the third part of the thesis, developed building blocks are used to implement the Capon beamformer algorithm. Two architectures are presented; the first architecture is based on a linear data flow, while the second architecture utilizes the single processing element architecture. The Capon beamformer implementation is going to be used in a channel sounder to determine the direction-of-arrival of impinging signals. Therefore it was important to derive and implement flexible and scalable architectures to be able to adapt to different measuring scenarios. The linear flow architecture was implemented and tested with measured data from the channel sounder. By analyzing each block in the design, a minimum wordlength design could be derived.
The fourth part of the thesis presents a design methodology for hardware implementation on FPGA.
The first part of the thesis deals with the implementation of complex valued division. Two architectures implementing a numerically robust algorithm for computing complex valued division with standard arithmetic units are presented. The first architecture is based on a parallel computation scheme offering high throughput rate and low latency, while the second architecture is based on a resource conservative time-multiplexed computation scheme offering good throughput rate. The two implementations are compared to an implementation of a CORDIC based complex valued division.
The second part of the thesis discusses implementation aspects of fundamental matrix operations found in many multiantenna algorithms. Four matrix operations were implemented; triangular matrix inversion, QR-decomposition, matrix inversion, and singular value decomposition. Matrix operations are usually implemented using large arrays of processors, which are difficult to scale and consume a lot of resources. In this thesis a method based on the data flow was applied to map the algorithms to scalable linear arrays. An even more resource conservative design based on a single processing element was also derived. All the architectures are capable of handling complex valued data necessary for the implementation of communication algorithms.
In the third part of the thesis, developed building blocks are used to implement the Capon beamformer algorithm. Two architectures are presented; the first architecture is based on a linear data flow, while the second architecture utilizes the single processing element architecture. The Capon beamformer implementation is going to be used in a channel sounder to determine the direction-of-arrival of impinging signals. Therefore it was important to derive and implement flexible and scalable architectures to be able to adapt to different measuring scenarios. The linear flow architecture was implemented and tested with measured data from the channel sounder. By analyzing each block in the design, a minimum wordlength design could be derived.
The fourth part of the thesis presents a design methodology for hardware implementation on FPGA.
Department/s
- Department of Electrical and Information Technology
Publishing year
2006
Language
English
Document type
Dissertation
Publisher
Department of Electroscience, Lund University
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Keywords
- Beamforming
- MIMO
- FPGA
- Implementation
- Hardware
- Matrix
- Inversion
- QR-decomposition
- SVD
- Capon
- Signal processing
- Signalbehandling
- Electronics
- Elektronik och elektroteknik
- Elektronik
- Telecommunication engineering
- Telekommunikationsteknik
- Electronics and Electrical technology
Status
Published
Supervisor
- Viktor Öwall
Defence date
17 February 2006
Defence time
10:15
Defence place
Room E:1406, E-building, Ole Römers väg 3, Lund Institute of Technology
Opponent
- Peter Koch (Associate Professor)