Fixed-point implementation of a robust complex valued divider architecture

Summary, in English

In this paper a fixed-point implementation of robust complex valued divider architecture is presented. The architecture uses feedback loops and time multiplexing strategies resulting in a fast and area conservative architecture. The architecture has good numerical properties and the result is accurate to less than one ulp. A combination of low latency and high throughput rate makes the architecture ideal for modern high speed signal processing applications. The complex valued divider architecture was implemented and tested on a Xilinx Virtex-II FPGA, clocked at 100MHz, and can easily be ported to an ASIC. The FPGA implementation is used as a core component in a matrix inversion implementation

• Author: Fredrik Edman; Viktor Öwall
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2005
• Language: English
• Pages: 143-146
• Publication/Series: [Host publication title missing]
• Links: http://dx.doi.org/10.1109/ECCTD.2005.1522930
• Document type: Conference paper
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Keywords: feedback loops; fixed-point implementation; ASIC; high speed signal processing applications; time multiplexing; 100 MHz; matrix inversion; Xilinx Virtex-II FPGA; complex valued divider architecture
• Conference name: European Conference on Circuit Theory and Design (ECCTD), 2005
• Conference date: 2005-08-28 - 2005-09-02
• Conference place: Cork, Ireland
• Status: Published
• ISBN/ISSN/Other: ISBN: 0-7803-9066-0